1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to a non-volatile semiconductor memory device in which characteristics of a memory cell changes with increase in the number of times of data rewriting. More particularly, the present invention relates to a configuration for performing a data rewriting operation in a non-volatile semiconductor memory device.
2. Description of the Background Art
In a non-volatile semiconductor memory device, writing (programming) or erasure is performed by injecting or ejecting electric charges to or from a floating gate or silicon nitride layer (SixNy), which is electrically insulated, and provided between a word line (control gate) and a semiconductor substrate, to change a threshold voltage of a memory cell transistor.
By changing an electric charge quantity accumulated in a floating gate or a silicon nitride layer, a threshold voltage of a memory cell continuously changes. Therefore, by setting the number of segmented regions of the threshold voltage from conventional two regions to four or eight regions, 2-bit data or 3-bit data can be stored in one memory cell. Such a memory storing data of multiple bits in one memory cell (memory cell transistor) is generally called a multi-valued memory.
FIG. 32 indicates a distribution of threshold voltages of a multi-valued memory. In FIG. 32, the threshold voltage region is divided into four regions by read voltages VRW0, VRW1 and VRW2 and 4-valued or 4-level data (2-bit data) is stored in one bit memory cell.
A read voltage represents a voltage applied to the control gate of a selected memory in reading data stored in the memory cell.
In FIG. 32, the abscissa reads values of a threshold voltage of a memory cell transistor, and the ordinate indicates the number of bits. In such 4-valued memory, 2-bit data of xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c00xe2x80x9d or xe2x80x9c01xe2x80x9d is stored in one memory cell. In order to perform correct reading/writing of data to/from the memory cell, restriction is imposed on distribution region of threshold voltages of memory cell transistors corresponding to the respective storage data. A threshold voltage of a memory cell transistor storing data xe2x80x9c11xe2x80x9d is defined to lie between a write verify voltage VWV0 and an upper foot verify voltage VOP0. A threshold voltage of a memory cell transistor storing data xe2x80x9c10xe2x80x9d is defined to lie between a write verify voltage VWV1 and an upper foot verify voltage VOP1.
A threshold voltage of a memory cell transistor storing data xe2x80x9c00xe2x80x9d is defined to lie between a write verify voltage VWV2 and an upper foot verify voltage VOP2. The lower limit of the threshold voltage of the memory cell transistor storing data xe2x80x9c01xe2x80x9d is defined by a write verify voltage VWV3.
Accordingly, a threshold voltage of a memory cell transistor storing data xe2x80x9c11xe2x80x9d lies in the lowest threshold voltage region and a threshold voltage of the memory cell transistor storing data xe2x80x9c01xe2x80x9d lies in the highest threshold voltage region.
FIG. 33 is a sectional diagram showing an example of a structure of a non-volatile memory cell. In FIG. 33, the memory cell includes: impurity regions S and D formed, spaced from each other, at a surface of a semiconductor substrate region SUB; a floating gate FG formed above a surface of a substrate region between impurity regions S and D with an insulating film not shown interposed in between; and a control gate CG formed in an upper layer above floating gate FG with an interlayer insulating film interposing in between.
Control gate CG is formed being integrated with a word line. Impurity regions S and D serve as source and drain regions, respectively. Floating gate FG is electrically isolated from the surroundings and accumulates electric charges according to storage data.
The non-volatile memory cell is constituted of one stacked gate field effect transistor.
In data reading, read voltages VRW0, VRW1 and VRW2 are applied in a prescribed sequence to control gate CG. Source region S is set to ground voltage level and drain region D is supplied with a prescribed read voltage (for example, 2.0 V). When a threshold voltage of the memory cell is lower than a read voltage applied to control gate CG, a channel is formed between the source and drain regions in the memory cell to cause a current to flow from the drain region to the source region.
The drain region D is connected to a data line generally called a bit line and discrimination on stored data is made according to whether or not a current flows through the bit line. In data reading, for example, read voltages VRW0 to VRW2 are sequentially applied in a prescribed sequence. When read voltages VRW0 to VRW2 are applied, it is determined whether or not a current flow through a bit line and storage data in a memory cell is identified according a result of determination.
If no current flows through a memory cell transistor even when any of read voltages VRW1 and VRW2 is applied, it is determined that data xe2x80x9c01xe2x80x9d is stored in the memory cell. On the other hand, if no current flows when read voltage VRW1 is applied, while a current flows when read voltage VRW2 is applied, it is determined that data xe2x80x9c00xe2x80x9d is stored in the memory cell.
If a current flows through a bit line when read voltage VRW0 is applied, while no current flows when each of read voltages VRW1 and VRW2 is applied, it is determined that data xe2x80x9c11xe2x80x9d is stored in the memory cell.
2-bit data is generated according to the results of determination and read out externally.
In data writing (programming) and erasing, in order to verify whether or not the writing/erasing is correctly performed, a verify voltage is applied to the control gate of the memory cell. In FIG. 33, there are also shown both of a control gate voltage and a bit line voltage applied in the verifying operation. A voltage in a range from 1.0 V to 6.0 V is applied to the control gate according to an operating mode and a voltage in the range from 0.5 V to 2.0 V is applied to the bit line (drain region D) according to an operating mode.
In a non-volatile semiconductor memory device, writing/erasing is implemented by moving electric charges through an insulating film immediately below a floating gate to change the electric charge quantity of the floating gate. Write (programming) characteristics or erasure characteristics of such a memory cell single is greatly varied by an influence of a film quality of the insulating film below the floating gate. Therefore, if a one shot writing pulse is generated in accordance with an externally applied write instructing signal as is done in a dynamic random access memory (DRAM) or a static random access memory (SRAM), writing and erasure cannot be performed such that threshold voltage of a memory cell falls within a prescribed range with sufficient correctness.
Therefore, it is needed to control a threshold voltage of a memory cell using an internal controller. As an example of control of a threshold voltage, a case is considered in which as shown in FIG. 34, electrons e are injected to floating gate FG from semiconductor substrate region SUB through Fowler-Nordheim (FN) tunneling phenomenon, thereby raising a threshold voltage of a memory cell transistor. Here, an operation of raising a threshold voltage of a memory cell is defined as writing.
In writing, a voltage in the range from 15 to 25 V is applied to control gate CG and source region S and drain region D is maintained at ground voltage level. In this state, a high electric field is applied between substrate region SUB and control gate CG to cause a FN tunneling phenomenon. Accordingly, electrons, e, flow through the insulating film between floating gate FG and substrate region SUB and are accumulated in floating gate FG and to raise the threshold voltage of the memory cell transistor.
Now, a case is considered in which a write pulse with a prescribed constant width at a prescribed constant voltage level is applied to control gate CG. In this case, as shown in FIG. 35, due to differences in characteristics among memory cells, a memory cell fast in writing has a threshold voltage attaining 5.0 V, while a memory cell slow in writing has a threshold voltage attaining 3.0 V. Herein, in FIG. 35, the ordinate indicates the number of bits and the abscissa indicates values of a threshold voltage Vth. The memory cell fast in writing, or the fast writing memory cell signifies a memory cell having a threshold voltage changed even greater under the same writing condition, as compared to the memory cell slow in writing, or the slow writing memory cell.
For memory cells with such varied write characteristics, the following procedure is required in order to confine the threshold voltages within a voltage region between 3.5 V and 3.9 V corresponding to data xe2x80x9c00xe2x80x9d of a multi-valued memory shown in FIG. 32.
Step 1:
First, a write pulse is applied with which a threshold voltage of the fastest memory cell does not exceed 3.9 V. Memory cells have characteristics as shown in FIG. 35 and threshold voltages of the memory cells distribute in the range, for example, from 1.9 V to 3.9 V by the first write pulse, as shown in FIG. 36.
Next, it is determined whether or not a threshold voltage exceeds 3.5 V on all of memory cells subject to writing, and a memory cell with a threshold voltage of 3.5 V or higher is excluded from writing targets (a verify operation).
Step 2:
Next, a write pulse, with which a threshold voltage of the fastest memory cell among memory cells having threshold voltages not exceeding 3.5 V in the first writing does not exceed 3.9 V, is applied to the control gates of memory cells of write targets. That is, a write pule is applied with which a threshold voltage of the fastest memory cell among memory cells of interest rises by 0.4 V.
Next, it is again determined whether or not all memory cells subject to writing exceed 3.5 V and a memory cell with a threshold voltage of 3.5 V or higher is excluded from writing targets. In the second write pulse application, a threshold voltage of the slowest memory cell rises and in FIG. 37, a threshold voltage of the slowest memory cell rises up to 2.3 V.
The above process is repeated till a threshold voltage of the slowest memory cell rises to 3.5 V or higher. Finally, the threshold voltages of memory cells are distributed within the range from 3.50 to 3.9 V, as shown in FIG. 38.
In the writing, a write pulse is applied such that a threshold voltage of the fastest memory cell, among memory cells with threshold voltages of 3.5 V or lower, does not exceed 3.9 V. Therefore, differences in threshold voltage among memory cells attain 0.4 V at the maximum. Accordingly, when a threshold voltage of the slowest memory cell is 1.9 V as shown in FIG. 36, it is needed to repeat at least five times application of a write pulse, followed by a verifying operation for detecting write targets.
In a case where variations in characteristics among memory cells increase and in a case where a control range for a threshold voltage is required to be narrower, an increased number of times of repetition of application of write pulses followed by verify operations is required.
As for a slower memory cell, injection of a greater quantity of electric charges is required in order to cause the same voltage change in threshold voltage. That is, a more intensive write pulse is required to be applied in writing at the (N+1)-th time than in writing at the N-th time, where Nxe2x89xa72.
The following method can be considered for application of such a write pulse.
That is, a voltage level of a pulse is successively raised with a pulse width being kept constant. Here, in FIG. 39, the abscissa indicates the time, while the ordinate indicates a voltage. Both units of the coordinates are arbitrary (a.u).
Moreover, a method can be considered, as shown in FIG. 40, in which a pulse width of the write pulse is successively broadened. A further method can be considered, as shown in FIG. 41, in which a pulse width and voltage level of a write pulse are increased with increase in the number of times of writing. In each of FIGS. 40 and 41, the horizontal axis indicates the voltage in arbitrary units and the vertical axis indicates the time in arbitrary units.
As shown in FIG. 42, threshold voltages (Vth) of memory cells, after data is written, are distributed between write verify voltage VWV and upper foot verify voltage VOP. In detection of a write target, write verify voltage VWV is used. Verification is performed using upper foot verify voltage VOP after completion of writing.
In an operation, there arise variations in memory cell threshold voltage caused by a variation in read (and verify) voltage due to a variation in power supply voltage and a variation in operating temperature, and a variation in memory cell threshold voltage within an operation guaranteed period is also caused. In order to perform correct reading of data even if such variations occur, threshold voltage needs to be controlled such that margins are present between write verify voltage VWV (in the above example, 3.5 V) and lower side read voltage VRWL (in this example, 3.0 V), and between upper foot verify voltage VOP (3.9 V) and upper side read voltage VRWu (4.0 V).
A function of performing the above writing operation under the control of a controller provided in a memory chip is called xe2x80x9cauto-writing function.xe2x80x9d The controller is usually constituted of a CPU (central processing unit) and the write operation is performed on the basis of software.
In a non-volatile semiconductor device, an erase operation is performed prior to rewriting of data. In an erase operation, as shown in FIG. 43, a negative voltage in the range from xe2x88x9215 to xe2x88x9225 V is applied to control gate CG and source region S and drain region D are set to ground voltage level. In this case, substrate region SUB is also at ground voltage level and electrons e flows out from floating gate FG into substrate region SUB to lower a threshold voltage of a memory cell transistor. In such a state where electrons are extracted from the floating gate, there is caused an over erasure state that a threshold voltage of a memory cell assumes a negative value. In the over erasure state, since a memory cell is conductive even if a voltage of the control gate is at ground voltage level, a write-back operation raising the threshold voltage is performed after the erasing.
In the write-back operation, a threshold voltage is controlled such that the threshold voltage lies between write verify voltage VWV0 and upper foot verify voltage VOP0. The write-back state is called an erasure state, and usually corresponds to a state of the lowest threshold voltage, or a state where data xe2x80x9c11xe2x80x9d is stored.
In the erasing operation, memory cells storing data xe2x80x9c10xe2x80x9d, xe2x80x9c00xe2x80x9d and xe2x80x9c01xe2x80x9d have their threshold voltages lowered to be set to a state of storing data xe2x80x9c11xe2x80x9d. Therefore, there are memory cells with various threshold voltages. Erasure is performed collectively in a sector unit. In a case where there exists a memory cell with a threshold voltage of upper foot verify voltage VOP or higher, a pulse is applied with which a threshold voltage of the slowest memory cell among memory cells each with a threshold voltage of upper foot verify voltage VOP or higher attains upper foot verify voltage VOP or lower. Therefore, in erasure, since the maximum threshold voltage is lowered according to application of an erase pulse, a pulse width or voltage level of the erase pulse is successively lowered, contrary to the case of writing.
When threshold voltages of all memory cells of interest attain the upper foot verify voltage or lower, writing-back is performed to distribute threshold voltages of the memory cells between write verify voltage VWV0 and upper foot verify voltage VOP0 shown in FIG. 32. The write-back operation is the same as that in writing of data xe2x80x9c11.xe2x80x9d
In the erasure as well, accordingly, application of an erase pulse and an erase verify operation are performed on each data. The erase operation is also performed by the controller provided in a memory chip and an erasure operation performed under control of the controller is called an auto-erase function.
The control of such auto-writing and auto-erasure is set taking into account a change in memory cell characteristics due to erasure/writing, or rewriting of a memory cell. Since in writing/erasing of data on a memory cell, a high voltage is applied between a control gate and a substrate region, characteristics of the memory cell changes due to a change in property of an insulating film (tunnel insulating film) between a floating gate and the substrate region, trapping of an electric charge in the insulating film and others. The following is an example of automatic rewrite control taking into account a change in write/erasure characteristics due to such erasure/writing (rewriting).
FIG. 44 shows a change in write/erase characteristics of a memory cell due to rewriting. The ordinate indicates a threshold voltage Vth of a memory cell when a pulse is applied under predetermined conditions of a constant voltage and a constant time period, while the abscissa indicates the number of times of rewriting. In FIG. 44, xe2x80x9c1.E+nxe2x80x9d represents the +n-th power of 10. A filled circle symbol indicates a threshold voltage Vth after writing and an empty circle symbol indicates a threshold voltage after erasure.
As shown in FIG. 44, as the number of times of rewriting increases, threshold voltages Vth of a memory cell after writing and after erasure both increase.
FIG. 45 shows a distribution of threshold voltages after rewriting. In FIG. 45, the ordinate indicates the number of bits, while the abscissa reads values of a threshold voltage. A curve I shows a distribution of threshold voltages after completion of the first rewriting and a curve II indicates a distribution of threshold voltages after rewriting is performed one million times. Since a threshold voltage Vth of a memory cell increases by the order of 0.4 V after the number of times of rewriting reaches one million times, the curve II becomes a curve shifting in the direction of a higher voltage by 0.4 V relative to the curve I.
Accordingly, there arises a difference in threshold distribution between when a first write pulse is applied in the first rewriting and when a first write pulse is applied after one million times of rewriting.
FIG. 46 shows a distribution of threshold voltages in the case when the first write pulse is applied after one million times of rewriting. In FIG. 46, the abscissa indicates values of a threshold voltage, while the ordinate indicates the number of bits.
In FIG. 46, a memory cell, a threshold voltage of which reaches 3.9 V when a write pulse is applied one time in the first time rewriting, has the threshold voltage attaining 4.3 V when a first write pulse is applied thereto after one million times of rewritings, thus exceeding the upper limit value (the upper foot verify voltage) 3.9 V of a control range of a threshold distribution. Accordingly, in order to design a non-volatile semiconductor memory device to guarantee one million times of rewriting operations, it is required to set, taking into account the increase in threshold value by 0.4 V after one million times of rewriting, a threshold voltage of the fastest memory cell to b e lower than 3.5 V by application of the first writing pulse in the first time rewriting. With such a setting, the threshold voltage of the fastest memory cell is attains 3.9 V after one million times of rewriting, thereby enabling the threshold voltages to fall within a desired threshold voltage control range.
In this case, for a distribution of threshold voltages of memory cells, it is necessary to consider threshold voltage distribution ranges of both curves I and II shown in FIG. 45, and therefore, it is necessary to consider the variation of threshold voltage of 2.4 V as the threshold distribution width. Therefore, in the case where a threshold voltage shifts by 0.4 V by one write pulse, it is necessary to repeatedly perform application of the write pulse followed by verifying operation at least six times, leading to an increased write time.
In the case of erasure, a memory cell after one million times of rewriting demonstrates a slower erasure than a memory cell in the first time rewriting. That is, a threshold voltage distribution curve in application of an erasure pulse in the first rewriting of a memory cell subject to one million times of rewriting shifts in a higher threshold voltage direction by 0.4 V relative to a threshold voltage distribution curve of a memory cell after application of an erase pulse in the first time rewriting. Therefore, while a threshold voltage of a memory cell is prevented from falling outside a control range thereof by application of an erase pulse in the first erasure, threshold voltage Vth of the memory cell subject to one million times of rewriting stays in a higher level even after application of an erase pulse of the first time in the rewriting.
In this erasure as well, accordingly, in order to perform correct erasure after one million times of rewriting, it is needed to set an erase pulse, taking into account a threshold voltage distribution width of 2.4 V. Therefore, in a case of erasure as well, application of an erase pulse and a following erase verify operation are required to repeat more times by the number of times corresponding to increased variation width of threshold voltage, resulting in increased erasing time.
FIG. 47 shows a relationship between a change in threshold voltage when data is held in a memory cell and the number of times of rewriting. In FIG. 47, the ordinate indicates a change amount in threshold voltage xcex94Vth, while the abscissa indicates the number of times of rewriting. A change amount in threshold voltage xcex94Vth indicates a change in threshold voltage of a memory cell when a prescribed time elapses immediately after data writing. As shown in FIG. 47, as the number of times of rewriting increases, a change amount in threshold voltage xcex94Vth becomes larger, and accordingly, a threshold voltage is lowered.
As for a margin for correct reading of data, as shown in FIG. 48, it is required that a margin xcex94M for variations in power supply voltage and temperature and the change amount in threshold voltage xcex94Vth are secured between lower side read voltage VRW and write verify voltage VWV being the lower limit voltage of the threshold voltage
In the first time rewriting, change amount in threshold voltage xcex94Vth is 0.1 V or lower. Therefore, 0.2 V is sufficient for a difference between write verify voltage VWV and lower side read voltage VRW, with the assumption of 0.1 V for variation factors in lower side read voltage VRW due to power supply voltage and temperature and in threshold voltage of a memory cell.
After one million times of rewriting, however, change amount in threshold voltage xcex94Vth attains 0.4 V. Therefore, with consideration of variations caused by power supply voltage and temperature, 0.5 V is required for a difference xcex94M+xcex94Vth between write verify voltage VWV and read voltage VRW.
In a 4-valued non-volatile semiconductor memory device as shown in FIG. 32, it is assumed that read voltages VRW0, VRW1 and VRW2 are 2.0 V, 3.0 V and 4.0 V, respectively, in normal data reading. A difference between adjacent read voltages is 1.0 V. If consideration is given on a change due to power supply voltage and temperature of 0.1 Vxc2x72 and a change in threshold voltage after one million times of rewriting of 0.4 V, as shown in FIG. 49, it is required to confine a threshold voltage distribution immediately after writing within a control region of 0.4 V as a control region (control width) of a threshold voltage.
That is, in a case where a threshold voltage distribution after one million times of rewriting is limited within a region ranging from 3.5 V to 3.9 V as shown in FIG. 50, a threshold voltage Vth shifts by 0.4 V after data is held. In this case, since there is variations in data holding characteristics of memory cells, a threshold voltage region ranges from 3.1 V to 3.9 V. Accordingly, even if a threshold voltage distribution is broadened to 3.1 V after data is held, lower side read voltage VRW1 is at 3.0 V, thereby enabling a margin of 0.1 V to be secured.
In a case where data writing is performed to a memory cell in an initial stage of rewritings, a threshold voltage changes by only 0.1 V even after data is held. Accordingly, if a threshold voltage control range is determined in consideration of a change in threshold voltage after one million times of rewriting, for the memory cells at an initial stage of rewriting, the lower limit value of a threshold voltage distribution changes from 3.5 V to 3.4 V only as shown in FIG. 51. There still exists a margin of 0.4 V for lower read voltage VRW1, and there is fully sufficient margin.
In a non-volatile semiconductor memory, as described above, conditions for a write pulse and an erase pulse are set in data rewriting of a memory cell, in consideration of the worst case of a write/erase characteristics of a memory cell. The conditions are in common to all the subsequent rewritings irrespective of the number of times of rewriting. Thereby, in all of the rewritings, a margin is allowed to present between a read voltage and a threshold voltage distribution region, to prevent erroneous data reading.
When the number of times of rewriting is small, there exists a margin larger than necessary. Writing/erasure is performed according to pulse conditions with an excessive margin, leading to a problem that inherent performance of memory cells cannot be sufficiently made used of.
Particularly, in a case where a control width for a threshold voltage is narrowed, a change in threshold voltage caused by a write pulse becomes smaller, and therefore, the number of application times of write pulse increases to increase the write time and to accelerate degradation in an insulating film of a memory cell.
Moreover, a threshold voltage rises with increase in the number of times of rewritings. If the change in threshold voltage due to erasure pulse is increased to compensate for the increased threshold voltage, an erase pulse larger than necessary is applied at an initial stage of rewriting, memory cell characteristics might be possibly degraded. Furthermore, since a shift in threshold voltage is large, write-back pulse has to be applied much more times in write-back operation than in rewriting after one million times of rewriting, leading to degradation in memory cell characteristics and an increased erase time.
It is an object of the present invention to provide a non-volatile semiconductor memory device capable of reducing a time required for data rewriting.
It is another object of the present invention to provide a non-volatile semiconductor memory device capable of providing a margin according to characteristics of a memory cell to rewritten data.
It is still another object of the present invention to provide a non-volatile semiconductor memory device capable of performing rewriting of data while fully utilizing characteristics of a memory cell.
It is a further object of the present invention to provide a non-volatile semiconductor device having long lifetime memory cells, and capable of rewriting data at a high speed without damaging reliability of a memory cell.
A non-volatile semiconductor memory device according to a first aspect of the present invention includes: a plurality of memory cells for storing data in a non-volatile manner; a number of rewriting storage circuit for storing the number of times of rewriting of storage data in the plurality of memory cells; and a rewrite condition control circuit for setting a condition on a rewrite pulse including at least one of a write pulse for writing data and an erase pulse for erasing storage data in accordance with stored data in the number of rewriting storage circuit. The set condition for at least one of a write pulse and an erase pulse can be altered in accordance with the number of times of rewriting.
A non-volatile semiconductor memory device according to a second aspect of the present invention includes: a plurality of non-volatile memory cells for storing data in a non-volatile manner; a number of rewriting storage circuit for storing the number of times of rewritings of storage data in the plurality of non-volatile memory cells; and a write condition control circuit for, in rewriting data of the memory cells, setting a condition for a write pulse for writing data in accordance with the number of times of rewritings indicated by storage data in the number of rewriting storage circuit.
A non-volatile semiconductor memory device according to a third aspect of the present invention includes: a plurality of non-volatile memory cells for storing data in a non-volatile manner; a number of rewriting storage circuit for storing the number of times of rewriting of storage data in the plurality of non-volatile memory cells; and an erase condition control circuit for, in rewriting data of the memory cells, setting a condition for an erase pulse for erasing data in accordance with the number of times of rewriting indicated by storage data in the number of rewriting storage circuit.
By changing a set condition for a rewrite pulse including at least one of a write pulse and an erase pulse in accordance with the number of times of rewriting, a rewrite pulse in an optimal condition can be applied even in a case where characteristics of a memory cell is varied in accordance with the number of times of rewriting and there is no need to perform rewriting in a pulse condition accounting for a margin more than necessary. Rewriting can be performed in a rewrite time according to characteristics of a memory cell. Thus, a rewrite time can be reduced and memory characteristics can be prevented from degrading.
Furthermore, by changing a condition set for a write pulse in accordance with the number of times of rewriting, a write pulse in an optimal condition can be applied even in a case where characteristics of a memory cell is different in accordance with the number of times of rewriting. There is no need to perform rewriting in a pulse condition set accounting for a margin more than necessary. Rewriting can be performed in a write time according to characteristics of a memory cell. Thereby, a rewrite time can be reduced and a memory characteristic can be prevented from degrading.
Moreover, by changing a condition set for an erase pulse in accordance with the number of times of rewriting, an erase pulse in an optimal condition can be applied even in a case where characteristics of a memory cell is different in accordance with the number of times of rewriting. There is no need to perform erasure in a pulse condition set accounting for a margin more than necessary. Erasure can be performed in an erase time according to characteristics of a memory cell. Thereby, an erase time can be reduced and memory characteristics can be prevented from degrading.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.